● Fast Zero Power (FZP) design technique provides ultra-low power and very high speed
● Typical Standby Current of 17 to 18 μA at 25°C
● Innovative CoolRunner™ XPLA3 architecture combines high speed with extreme flexibility
● Based on industry"s first TotalCMOS PLD — both CMOS design and process technologies
● Advanced 0.35μ five layer metal EEPROM process
● 1,000 erase/program cycles guaranteed
● 20 years data retention guaranteed
● 3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface
● Full Boundary-Scan Test (IEEE 1149.1)
● Fast programming times
● Support for complex asynchronous clocking
● 16 product term clocks and four local control term clocks per function block
● Four global clocks and one universal control term clock per device
● Excellent pin retention during design changes
● Available in commercial grade and extended voltage (2.7V to 3.6V) industrial grade
● 5V tolerant I/O pins
● Input register setup time of 2.5 ns
● Single pass logic expandable to 48 product terms
● High-speed pin-to-pin delays of 5.0 ns
● Slew rate control per output
● 100% routable
● Security bit prevents unauthorized access
● Supports hot-plugging capability
● Design entry/verification using Xilinx or industry standard CAE tools
● Innovative Control Term structure provides:
● Asynchronous macrocell clocking
● Asynchronous macrocell register preset/reset
● Clock enable control per macrocell
● Four output enable controls per function block
● Foldback NAND for synthesis optimization
● Universal 3-state which facilitates "bed of nails" testing
● Available in Chip-scale BGA, Fineline BGA, and QFP packages. Pb-free available for most package types.
