● High-performance XC800 Core
● compatible with standard 8051 processor
● two clocks per machine cycle architecture (for memory access without wait state)
● two data pointers
● On-chip memory
● 8 Kbytes of Boot ROM, Library ROM and User routines
● 256 bytes of RAM
● 256 bytes of XRAM
● 2/4 Kbytes of Flash (includes memory protection strategy)
● I/O port supply at 2.5 V - 5.5 V and core logic supply at 2.5 V (generated by embedded voltage regulator)
● Power-on reset generation
● Brownout detection for IO supply and core logic supply
● 48 MHz on-chip OSC for clock generation
● Loss-of-Clock detection
● Power saving modes
● idle mode
● power-down mode with wake-up capability via real-time clock interrupt
● clock gating control to each peripheral
● Programmable 16-bit Watchdog Timer (WDT) running on independent oscillator with programmable window feature for refresh operation and warning prior to overflow
● Three ports
● Up to 17 pins as digital I/O
● 4 pin as digital/analog input
● 4-channel, 10-bit ADC
● support up to 3 differential input channel
● results filtering by data reduction or digital low-pass filter, for up to 13-bit results
● Up to 4 channels, Out of range comparator
● Three 16-bit timers
● Timer 0 and Timer 1 (T0 and T1)
● Timer 2 (T2)
● Periodic wake-up timer
● Multiplication/Division Unit for arithmetic operations (MDU)
● Capture and Compare unit for PWM signal generation (CCU6)
● A full-duplex or half-duplex serial interface (UART)
● Synchronous serial channel (SSC)
● Inter-IC (IIC) serial interface
● LED and Touch-sense Controller (LEDTSCU)
● On-chip debug support via single pin DAP interface (SPD)
Part 3D Model
