● High-speed 16-bit CPU (900/L1 CPU)
● Instruction mnemonics are upward-compatible with TLCS-90/900
● General-purpose registers and register banks
● 16 Mbytes of linear address space
● 16-bit multiplication and division instructions; bit transfer and arithmetic instructions
● Micro DMA: 4-channels (593 ns/2 bytes at 27 MHz)
● Minimum instruction execution time: 148 ns (at 27 MHz)
● Built-in RAM: 16 Kbytes
● Built-in ROM: 256 Kbytes Flash memory
● 4 Kbytes mask ROM (used for booting)
● External memory expansion
● Expandable up to 16 Mbytes (shared program/data area)
● Can simultaneously support 8-/16-bit width external data bus Dynamic data bus sizing
● 8-bit timers: 8 channels
● 16-bit timer/event counter: 2 channels
● General-purpose serial interface: 2 channels
● UART/ Synchronous mode: 2 channels
● IrDA ver1.0 (115.2 kbps) supported: 1 channel
● Serial bus interface: 1 channel
● I²C bus mode/clock synchronous Select mode
● 10-bit AD converter (built-in sample hold circuit): 8 channels
● Watchdog timer
● Special timer for clock
● Chip Select/Wait controller: 4 channels
● Interrupts: 45 interrupts
● 9 CPU interrupts: Software interrupt instruction and illegal instruction
● 26 internal interrupts:
● 10 external interrupts:
● Input/Output ports: 81 pins
● Standby function
● Three HALT modes: IDLE2 (programmable), IDLE1, STOP
● Clock controller
● Clock Gear function: Select a high-frequency clock (fc to fc/16)
● Special timer for CLOCK (fs = 32.768 kHz)
● Operating voltage
● Vcc = 2.7 V to 3.6 V (fc max = 27 MHz, flash memory read operation)
● Vcc = 3.0 V to 3.6 V (fc max = 27 MHz, flash memory erase/program operations)
● Package: 100-pin LQFP
Part 3D Model
