SPC565MZP56DR2 Datasheet PDF - NXP

●Overview

●The MPC565 is a member of the MPC500 family of microprocessors that implements the Power Architecture® instruction standard architecture. The MPC565 is integrated with a floating point unit, an advanced peripheral set and 1 MB of flash memory on a single chip. This combination is ideal for high-performance automotive applications as well as other control-intensive applications.

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●## Features

● 1 MB of internal flash memory (divided into two blocks of 512 KB)

● 36 KB static RAM

● Three time processor units (TPU3)

● A 22-timer channel modular I/O system (MIOS14)

● Three TouCAN modules

● Two enhanced queued analog system with analog multiplexors (AMUX) for 40 total analog channels. These modules are configured so each module can access all 40 of the analog inputs to the part

● Two queued serial multi-channel modules, each of which contains a queued serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART)

● A J1850 (DLCMD2) communications module

● A NEXUS debug port (class 3) – IEEE®ISTO 5001-1999

● JTAG and background debug mode (BDM)

●## Features