SN74LVC841APW Datasheet PDF - TI

●The SN74LVC841APW is a 10-bit bus-interface D Latch with 3-state outputs. It is designed for 1.65 to 3.6V VCC operation. The SN74LVC841A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. The ten latches are transparent D-type latches. The device has non-inverting data (D) inputs and provides true data at its outputs. A buffered OE\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components.

● Ioff Supports partial-power-down mode operation

● Supports mixed-mode signal operation on all ports

● Latch-up performance exceeds 250mA per JESD 17

● Green product and no Sb/Br