SN65LVDS388DBTR Datasheet PDF - TI

●description

●The ‘LVDS388 and ‘LVDT388 (Tdesignates integrated termination) are eight differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail.

●Eight Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard

●Integrated 110-ΩLine Termination Resistors on LVDT Products

●Designed for Signaling Rates†Up To 630 Mbps

●SN65 Version’s Bus-Terminal ESD Exceeds 15 kV

●Operates From a Single 3.3-V Supply

●Propagation Delay Time of 2.6 ns (Typ)

●Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns

●LVTTL Levels Are 5-V Tolerant

●Open-Circuit Fail Safe

●Flow-Through Pin Out

●Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch