P2020NXN2MHC Datasheet PDF - NXP

●Core Complex

● Dual (P2020) or single (P2010) high-performance Power Architecture® e500 cores

● Up to 1.33 GHz

● 32 KB L1 and 512KB L2 caches Networking Elements

● Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs)

● Four SerDes up to 3.125 GHz multiplexed across controllers supporting:

● Two PCI Express® interfaces

● Two Serial RapidIO® interfaces

● Two SGMII interfaces Accelerators and Memory Control

● Integrated security engine

● Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi, XOR acceleration Basic Peripherals and Interconnect

● Dual high-speed USB controllers (USB 2.0)

● eLBC, eSDHC, Dual I²C, DUART, PIC, DMA, GPIO Additional Features

● Package: 689-pin temperature-enhanced plastic BGA (TEPBGA2)

● 0C to 125C Tj -40C to 125C Tj option