MPC561MZP56R2 Datasheet PDF - NXP

●Overview

●The MPC561 is a high-speed 32-bit control unit that combines high-performance data manipulation capabilities with powerful peripheral subsystems. This MCU is built up from standard modules that interface through a common intermodule bus (IMB).

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●## Features

● Precise exception model

● Floating point

● Extensive system development support

● On-chip watchpoints and breakpoints

● Background debug mode (BDM)

● IEEE®ISTO 5001-1999 NEXUS class 3 debug interface

● True 5-volt I/O

● Two time processing units (TPU3) with 8 KB DPTRAM

● 22-channel MIOS timer (MIOS14)

● Two queued analog-to-digital converter modules (QADC64_A, QADC64_B) providing a total of 32 analog channels

● Three TouCAN modules (TOUCAN_A, TOUCAN_B, TOUCAN_C)

● One queued serial module with one queued SPI and two SCIs (QSMCM) 32 KB static RAM (CALRAM)

●## Features