●Introduction
●In dual voltage architectures, coordinated management of power supplies is necessary to avoid potential problems and ensure reliable performance. Power supply designers must consider the timing and voltage differences between core and I/O voltage supplies during power-up and power-down operations.
●Sequencing refers to the order, timing and differential in which the two voltage rails are powered up and down. A system designed without proper sequencing may be at risk for two types of failures. The first of these represents a threat to the long term reliability of the dual voltage device, while the second is more immediate, with the possibility of damaging interface circuits in the processor or system devices such as memory, logic or data converter ICs.
●Another potential problem with improper supply sequencing is bus contention. Bus contention is a condition when the processor and another device both attempt to control a bidirectional bus during power up. Bus contention also may affect I/O reliability. Power supply designers must check the requirements regarding bus contention for individual devices.
●Features
●Here VRTC is included in the STATIC12 (fixed 1.2V) group.
●TPS74801 and TPS74701
●• VOUT Range: 0.8 V to 3.6 V
●• 2% Accuracy Over Line/Load/Temperature
●• Programmable Soft-Start Provides Linear Voltage Startup
●• Stable with Any Output Capacitor ≥ 2.2 mF
●• Available in a Small 3-mm × 3-mm × 1-mm SON-10 and 5 × 5 QFN-20 Packages
●TPS71718
●• 150-mA Low-Dropout Regulator with Enable
●• Low Noise: 30 mV typical (100 Hz to 100 kHz)
●• Excellent Load/Line Transient Response
●• Small SC70-5, 2-mm × 2-mm SON-6, and 1,5-mm × 1,5-mm SON-6 Packages
