74AHC30PW Datasheet PDF - NXP

●General description

●The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

●The 74AHC30; 74AHCT30 provides an 8-input NAND function.

●Features

●■ Balanced propagation delays

●■ All inputs have Schmitt-trigger actions

●■ Inputs accept voltages higher than VCC

●■ Input levels:

●   ◆ For 74AHC30: CMOS level

●   ◆ For 74AHCT30: TTL level

●■ ESD protection:

●   ◆ HBM JESD22-A114E exceeds 2000 V

●   ◆ MM JESD22-A115-A exceeds 200 V

●   ◆ CDM JESD22-C101C exceeds 1000 V

●■ Multiple package options

●■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C